The invention is generally directed to the field of digital computer systems, and more particularly to the field of arrangements for simulating the functioning of integrated circuits. The invention provides a new and improved interface subsystem for use in connection with a simulation system, such as Verilog, to interface simulation tests which are written in a high-level programming language, such asxe2x80x9cC,xe2x80x9d its derivatives and extensions, to a simulation model provided by, illustratively, Verilog.
Electrical engineers typically design electronic circuits, such as integrated circuit chips, using circuit libraries which include definitions for standard circuit components calledxe2x80x9ccells.xe2x80x9d Using a hardware description language (xe2x80x9cHDLxe2x80x9d), a circuit designer will generate a detailed functional description of the desired behavior of the circuit being designed, which describes in detail the output signals to be generated by the circuit in response to input signals provided thereto. From the description, various cells to be used in the circuit are selected, and the interconnections among the selected cells are generated to define the actual circuit. Generating a design for an electronic circuit using an HDL is generally similar to generating a computer program for execution by a computer, except that the HDL""s that are used are typically specialized to the field of electronic circuit design.
After a design has been developed for the circuit, and preferably before the circuit has actually been implemented, the design will be simulated, using the description provided by the designer, to verify that it will operates in a correct manner. A number of systems are available for simulating the operations of an electronic circuit design using an HDL description of the circuit, one such system comprising the well-known Verilog system. The simulation tests which are used in verification will generally not be designed by the circuit designer; typically, simulation tests will be designed by verification engineers who specialize in designing such tests. The simulation tests can be constructed using the HDL in which the circuit was designed.
However, as noted above, HDL""s are typically specialized, and it would be advantageous to allow verification engineers to generate verification tests used to simulate a circuit design using better-known programming languages, such as high-level programming languages which are generally used in programming computers.
The invention provides a new and improved interface for use in connection with a simulation system, such as Verilog, particularly to interface simulation tests which are written in a high-level programming language, such asxe2x80x9cC,xe2x80x9d its derivatives and extensions, to a simulation model provided by, illustratively, Verilog.
In brief summary, in one aspect the invention provides an interface subsystem for use in a system including one or more simulation systems to facilitate simulation of one or more simulation models under control of one or more tests. The interface subsystem allows the tests and simulation systems to transfer information therebetween and enables said tests to control the simulation systems in simulating the simulation model during a simulation run. The simulation systems include transactors which provide information to the simulation model at the beginning of a simulation run, pause a simulation run in response to detection of a selected event, and generate simulation result information. The interface subsystem includes, associated with each test, a simulation information generator, a simulation control indicator generator, and a information receiver; associated with each simulation system an information receiver associated with each transactor and a simulator interface module; and an interface core. The a simulation information generator provides simulation information to be transferred to said simulation system for use during a simulation run and the simulation control indicator generator generates a simulation control indicator for controlling said simulation system. Each test""s information receiver receives simulation result information generated during a simulation run. Each simulation system""s simulator interface module (a) receives simulation information and providing the received simulation to an information receiver for use by the associated transactor, (b) receives simulating result information from said at least one transactor to be provided to said at least one test, and (c) controls said at least one simulation system to initiate a simulation run in response to receipt of a control indicator. Each transactor""s information receiver receives simulation information for use by the associated transactor during a simulation run. The interface core transfers (a) simulation information from a test to the simulator interface module of a simulating system for provision to one transactor""s information receiver for use by a transactor during a simulation run, (b) said simulation control indicator to the simulator interface module of a simulation system for controlling the simulation system in a simulation run, and (c) simulation result information from the transactors to the tests during a simulation run.